Principal Engineer - Digital IC Design

Job title: Principal Engineer - Digital IC Design

About the Role As a member of Marvell's digital design team, you will help define sub-system architecture and RTL for next-generation high-speed DSPs and PHYs, collaborating across architecture, verification, and back-end teams to deliver cutting-edge designs.

What You'll Do

• Define the sub system architecture, micro-architecture and register specifications for highly complex SoCs, and drive specification writeups with the architecture team
• Develop efficient RTL using SystemVerilog, perform synthesis, and collaborate with backend resources
• Integrate internal and external vendor IPs
• Design, debug, and support ICs, IPs and block DFT, ensuring all quality criteria are met
• Work closely with architecture, floorplanning, backend, verification, DFT, STA teams and other cross functional teams to produce high quality hardware
• Participate in various aspects of chip design RTL development, DFT design, synthesis, static timing analysis, formal equivalence, RTL lint, cross clock domain (CDC) analysis and functional verification
• Work with the Verification team on pre-silicon verification tasks
• Assist in design automation of various aspects of the CAD EDA flow
• Collaborate with post-silicon and software teams for prototype bring-up and performance tuning
• Collaborate with cross-functional teams consisting of architects, designers, verification, physical design, and software/firmware engineers; provide mentorship to junior team members

What We're Looking For

• MS/PhD in EE or related technical field and 10 years of professional experience
• Fluent in RTL coding design techniques; DFT, resets, LEC, Lint, etc
• Experience working with multi-clock designs
• Experience on synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification
• Experience on Test structures for DFT, IP Integration, Fault models, coverage improvement techniques
• Well-versed in all stages of the ASIC design flow (including specification, architecture and design implementation, prototype bring-up)
• Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment
• Must be a team player with a strong can-do attitude
• Effective communication and presentation skills
• Design experience in high speed (>1 GHz)/high-performance DSP products is highly desirable
• Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is highly desirable

Compensation & Benefits

• Salary range: 64,500 - 86,000 EUR per annum
• With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity.
• All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.