About this role
Job title: Principal Engineer, Design Verification
About the Role Marvell's Data Centre Engineering Group seeks a Principal Engineer in Design Verification to architect and implement verification environments for high-performance data centre silicon. The role focuses on IP verification for custom silicon, ensuring correctness, performance, and coverage.
What You'll Do
- Architect and implement simulation test benches in UVM.
- Develop and execute test plans to verify correctness and performance of the design.
- Own and debug simulation failures to root cause problems.
- Collaborate closely with logic designers for test plan development, execution, debugging, coverage closure, and gate-level simulations.
What We're Looking For
- Bachelor's degree in CS/EE with 13+ years or Master's degree with 11+ years relevant experience.
- Strong background in IP verification, including methodology and testbench development.
- Proficient in Verilog, SystemVerilog, UVM, and C/C++.
- Solid understanding of verification methodologies: object-oriented programming, white-box/black-box testing, directed/random testing, coverage analysis, and gate-level simulations.
- Experience in Unix/Linux environments; scripting in Shell, Perl, or Python is a plus.
- Strong analytical and problem-solving skills; ability to manage multiple tasks in a fast-paced environment.
- Excellent communication, interpersonal, and teamwork skills; capable of interfacing at all levels within and outside the organization.
- Proactive in problem-solving and quality improvement initiatives.
- Experience in working on processor-based subsystems.
- Experience in working on HW Security is desirable.
Nice to Have
- Experience in hardware security is desirable.
Compensation & Benefits
- With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity.