PDK Engineer

About the Role Join Skyworks to enable world-class analog and mixed-signal design across heterogeneous process technologies—from GaAs/HBT to advanced 22nm and below. You will develop, validate, and release process design kits (PDKs) with accurate models, verified rule decks, and design guidelines to empower design teams to deliver complex products on time and with high quality. What You'll Do

• Develop and maintain PDK components: device models, pcells, technology files, and DRC/LVS/PEX rule decks
• Validate PDK releases against foundry documentation, reference structures, and internal design benchmarks
• Support HBT and GaAs process technologies—device characterization, model fitting, and layout-aware design rules for RF applications
• Enable foundry technologies at 22nm and above nodes for analog/mixed-signal design IPs
• Collaborate with foundries, internal process teams, and design groups to resolve PDK gaps and drive closure on open issues
• Build regression and QA infrastructure for PDK releases; maintain version control and release notes What We're Looking For
• M.Tech/M.E./M.S. in EE/CE or equivalent from a reputed university
• 3–5 years in PDK development, technology enablement, and CAD/methodology for analog/mixed-signal design
• Hands-on experience with Cadence Virtuoso flows (OA database, pcells, techfile, rule deck integration)
• Strong understanding of semiconductor device physics for analog/RF: MOS, bipolar/HBT, passive structures, and process corners
• Experience with DRC/LVS/PEX deck development or validation in a production PDK environment
• Proficiency in SKILL and/or Python for PDK automation and QA scripting
• Ability to read and interpret foundry design manuals, DRMs, and model documentation
• Detail-oriented approach to release management, versioning, and issue tracking Nice to Have
• Direct experience with GaAs or SiGe HBT PDKs for power amplifier, LNA, or switch applications
• Familiarity with BAW/SAW filter process modules or integrated passive device (IPD) technologies
• Experience enabling 22nm and up nodes for analog/RF (thick metals, inductors, varactors, high-voltage devices)
• Background in device modeling or correlation between simulation and silicon data
• Exposure to foundry interfaces
• Understanding of RF-specific layout effects and EM-aware PDK considerations