Memory Design Engineer

Job title: Memory Design Engineer

About the Role

The Senior IP Engineer will report to the Director of Design Enablement and will play a critical role in supporting the Design Enablement team. This role will perform semiconductor device layouts in EDA software environment for semiconductor technology development and device modeling, and support the release of Foundry mask manufacturing requirements for a global design community. You will design and verify standard IP memories including Single-Port SRAM, Register File, ROM, One-Time-Programmable, EEPROM, and FLASH to support the development of our BCD technology and global design community.

What You'll Do

• Design NVM, VM, driver circuit, and digital IP.

• IP in silicon test and validation.

• Coordinate design requirements, macro floor planning, and layout design.

• Characterization and standardization of memory/digital IP for global design use within a custom PDK environment.

• Documentation development and publishing of IP specifications and application use cases.

• What We're Looking For

• A qualified candidate requires a BSEE with a minimum of 2 years of experience in the industry. Experience must include memory and mix-signal transistor-level design, circuit verification, and silicon testing.

• Applications knowledge of: Digital components (logic, memory, EEPROM, TAP controllers, JTAG, FPGA, serial data communication protocols, microprocessors and microcontrollers).

• Ability to develop Memory test/validation plans.

• Ability to characterize Memory/Standard Cells in standard liberty format.

• Ability to work with design teams on memory debug and diagnostics.

• EDA Skills/knowledge includes fundamental experience with Cadence tool flows (Virtuoso, Genus compiler, Innovus, Xcellium, Modus Test, and Calibre) and IP characterization.