About this role
Memory Circuit Design Verification Engineer
We are looking for an experienced Memory Circuit Design Verification Engineer to verify and validate complex memory circuits and full-chip memory designs. The candidate will be responsible for pre-silicon verification, circuit simulation, functional validation, timing analysis, debugging, and verification-flow development for advanced memory technologies.
The role involves working with memory design, circuit design, characterization, and design verification teams to ensure functional correctness, timing compliance, and robust operation across process, voltage, and temperature (PVT) conditions.
Key responsibilities
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Perform full-chip and block-level verification of memory circuits and memory IP.
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Develop and execute verification plans, test cases, test vectors, and simulation regressions.
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Perform gate-level simulations with timing delays and analyze logic schematics.
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Run SPICE and FastSPICE simulations to verify circuit functionality and critical memory timing parameters.
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Analyze read/write operations, setup/hold timing, access time, critical data paths, and timing margins.
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Verify memory architectures, including SRAM, DRAM, LPDDR, DDR, and emerging memory technologies, depending on project requirements.
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Debug functional failures, timing violations, waveform mismatches, and circuit-level issues.
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Perform PVT, corner, and speed-grade analysis to validate design robustness.
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Develop and maintain testbenches, verification environments, and automation scripts.
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Collaborate with memory circuit designers to identify root causes and resolve design issues.
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Analyze regression results, improve functional coverage, and optimize verification methodologies.
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Support verification sign-off and documentation of results.
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These responsibilities align with published memory verification roles emphasizing full-chip simulation, critical timing analysis, SPICE-based verification, and regression automation.
Required technical skills
- Skill area Relevant skills / keywords
- Memory fundamentals SRAM, DRAM, DDR, LPDDR, memory architecture
- Circuit verification SPICE, FastSPICE, transistor-level and gate-level simulation
- Digital verification Verilog, SystemVerilog, testbench development, UVM where applicable
- Timing analysis Setup/hold, access time, critical path, timing margins
- Circuit analysis CMOS, transistor-level schematics, waveform analysis
- PVT verification Process corners, voltage and temperature variations, speed grades
- Debug and regression Functional debugging, failure analysis, coverage, regression management
- Scripting Python, Perl, Tcl or Shell scripting
- EDA tools PrimeSim, FineSim, Spectre, HSPICE, Xcelium, SimVision, WaveView; tool requirements vary by client
The combination of SPICE/FastSPICE, memory timing, and gate-level verification is particularly relevant to current memory circuit verification openings.
Preferred qualifications
- Experience in memory circuit design verification or custom memory IP validation.
- Understanding of analog/mixed-signal circuit behavior and CMOS/FinFET technologies.
- Experience with full-chip analog SPICE simulation and timing sign-off.
- Familiarity with SRAM/DRAM critical timing concepts and memory operation sequences.
- Knowledge of memory compiler verification, characterization, and Liberty (.lib) model validation.
- Experience with automation frameworks and verification-flow improvement.
- Strong analytical, debugging, communication, and cross-functional collaboration skills.
Must-have skills
SRAMDRAM
Good-to-have skills
Memory Design