About this role
Machine Learning Engineer (ML for Chip Design) (US Candidates Only)
San Jose, California, United States
Full-Time
On-Site
Job Description:
Responsibilities
- Train, fine-tune, and post-train large language models for chip design and verification tasks using supervised fine-tuning, human-feedback training, and reinforcement learning.
- Build and maintain data pipelines, including data collection, cleaning, and synthetic data creation.
- Design strong evaluation methods to measure model accuracy and AI agent performance.
- Work with research scientists, systems engineers, and chip-design experts to turn research ideas into production AI agents.
- Use large GPU clusters to run experiments, study model behavior, and improve AI code-generation workflows.
Requirements
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B.S., M.S., or PhD in Computer Science, Electrical Engineering, or a related field.
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Alternatively, 2–10 years as an ML engineer, or a recent PhD graduate.
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Hands-on experience training or fine-tuning LLMs using Python and PyTorch.
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Familiarity with distributed GPU training and inference (vLLM, SGLang, CUDA, Ray).
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Able to work on-site 5 days a week in San Jose.
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Skills Required
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LLM fine-tuning (SFT, RLHF) & post-training
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Python & PyTorch
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Hugging Face Transformers
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Distributed GPU training/inference (vLLM, SGLang, CUDA, Ray)
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Data pipelines & synthetic data
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Model evaluation frameworks
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Agentic AI workflows
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Hardware design languages (RTL, Verilog, SystemVerilog), an advantage