Lead RTL Design Engineer

A Lead RTL Design Engineer at Advanced Micro Devices in Bangalore, India, will be part of the SoC Design team and hold technical responsibility for SoC design and integration efforts involving AMD and third-party IPs. This role collaborates closely with IP development, verification, front-end integration, and physical design teams throughout the SoC development cycle.

Responsibilities

• Lead SoC-level design and integration, including integration of IPs, SoC fabric, voltage and clock crossings, resets, fuses, and I/O.
• RTL design and coding for SoC logic and features, and manage SoC power design and power implementation activities.
• Conduct static verification including RTL lint, clock domain crossing (CDC), reset domain crossing (RDC), and power checks.
• Perform connectivity checks, debug simulation and integration issues spanning multiple IPs in collaboration with verification teams.
• Support top-level synthesis and collaborate with physical design teams for full-chip implementation.
• Lead one design domain (e.g., integration, power, CDC/RDC, connectivity, etc.).

Requirements

• Verilog RTL development experience in CPU, SoC, or ASIC environments.
• Strong understanding of SoC integration, SoC architecture, and system interconnect protocols such as AXI and PCIe.
• Experience with UPF and low-power methodologies.
• Familiarity with static timing analysis (STA) and physical design interaction and implementation requirements.
• Knowledge of scripting languages such as Tcl, Perl, Ruby, or Shell.
• Knowledge of formal verification techniques and tools.
• 8+ years of SoC design and Verilog RTL development experience.
• BE/B.Tech/ME/M.Tech in ECE/EEE or equivalent.
• Personal attributes: self-driven and able to work independently; strong written and verbal communication skills; strong problem-solving ability.