IP Enablement Application Engineer

Job title: IP Enablement Application Engineer

About the Role Intel Foundry Services Aerospace, Defense & Government (ADG) IP Enablement Application Engineer provides comprehensive technical support to IP integration challenges, engaging with IP design teams and customers across all phases of IP development—from architecture through post-silicon validation and debug. This role emphasizes customer obsession with hands-on debugging and rapid issue resolution across design domains.

What You'll Do

• Provide comprehensive technical support to Intel Foundry Services customers on IP integration issues, working with design teams and customers to solve complex challenges remotely or onsite.
• Own assigned IPs and guide customers in integrating Intel IPs into SoCs, delivering expert technical support throughout the integration lifecycle—from architecture to post-silicon validation.
• Drive resolution of customer issues related to IP collateral generation, logic design verification, IP release, and integration in SoC environments.
• Collaborate with cross-functional teams to develop SoC and IP integration methodologies and best practices; ensure IP collaterals are generated and delivered according to customer requirements and industry standards.
• Engage with IP development teams to ensure all IP collaterals are produced per customer requirements; coordinate with foundry customers' design teams, IP providers, and EDA vendors on issue resolution.
• Gather and document customer requirements up front, work with IP design teams to address requests, and provide training materials to enable effective debugging.
• Create application notes, documentation, and deliver technical training presentations to customers and internal teams.
• Drive quality improvements in design kits and documentation; support debugging and problem-solving activities in collaborative team environments; contribute to methodologies that boost IP integration productivity and customer satisfaction.
• Travel to customer sites as required to support deployments and training.

What We're Looking For

• Minimum Qualifications: US Citizenship required; ability to obtain a US Government Security Clearance; Bachelor's degree in Electrical Engineering, Computer Science, or a STEM-related field; 2+ years of experience in SOC IP Integration; 3+ years of combined experience in RTL design and DFT using Verilog/SystemVerilog; experience in ASIC or SoC development.
• Preferred Qualifications: Active US Government Security Clearance with a minimum of Secret level; Postgraduate degree in Electrical Engineering, Computer Science, or a STEM-related field; experience with IO interfaces including ADPLL, GPIO, DDR, LPDDR, PCIe, USB, USB Type-C, Ethernet, etc.; experience with VCS, Verdi, Spyglass or equivalents; experience with IP integration and design flow challenges within subsystems and SOCs; experience with IP development; experience with scripting languages such as Perl, Tcl, and Python.

Nice to Have

• Additional qualifications from the Preferred Qualifications (e.g., security clearance, advanced degree, broader IO/interface experience, and scripting proficiency).

Compensation & Benefits

• Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications.
• Direct customer engagement and technical leadership in advanced memory design.
• Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio.
• Competitive compensation and professional development in memory design methodologies and foundry services.
• Direct impact on national security through advanced memory semiconductor solutions.