Intern - IC Design Exploration

An internship with Advanced Micro Devices in Singapore invites you to explore IC design through hands-on experience across multiple disciplines. You will join the SerDes Technology team and collaborate with engineers globally, gaining insight into analog, digital, verification, and post-silicon activities. The program is designed to help you understand the differences between disciplines and to inform your path after graduation.

You will begin by building a solid foundation in IC design, getting to know the Singapore Design Team, and learning to work both independently and as part of a distributed team. Over the next few months, you will develop soft skills such as communication and presentation, participate in technical discussions and knowledge-sharing sessions, and learn to make engineering judgments. You will work on projects aligned with your specialization and have opportunities to explore cross-functional experiences such as RTL, layout, STA, and verification. Throughout the internship, you are encouraged to participate in company and department events and other activities.

Specializations may include one or more of the following areas:

• Analog design: high-speed analog and mixed-signal circuit and auxiliary block design for 112 Gbps and above in advanced technology nodes (3nm, 7nm); use, simulate, and analyze EDA-generated data; learn SERDES architecture (transmitter, receiver, PLL); basic scripting and programming; familiarity with IC design tools; understanding the IC design flow; cross-functional experiences with RTL, Layout, STA, and Verification.
• Analog layout implementation: layout of high-speed circuits and auxiliary blocks; perform LVS/DRC checks; understand Process Design Rules and metal schemes; scripting and programming; familiarity with IC design tools; cross-functional experiences with RTL/Circuit/PnR/STA/Verification.
• Analog static timing analysis: develop timing models for advanced nodes; build constraints with design and layout teams; tune design hierarchy and generate timing models; maintain timing model databases; evaluate EDA tools and flows.
• Digital design and implementation: design digital logic blocks in Verilog (RTL); low-power design explorations; develop testbenches and functional verification; UNIX/Linux in EDA tools; plan synthesis and timing closure on complex ICs; collaborate across Logic, Circuits, DFT, and Layout; ensure DRC/DFM compliance.
• Digital verification: functional verification of SerDes and/or security IP; testbench design in SystemVerilog/UVM and Python-based frameworks; manage regressions, debug and resolve design bugs; perform coverage analysis; contribute to automation and AI/ML-enhanced workflows.
• Post-silicon validation: SerDes bring-up, validation, and performance optimization; develop validation methodologies and automation scripts; work with design engineers to debug silicon issues; tune configurations and validate against industry standards in PVT environments.

Preferred skills include a solid foundation in digital logic, experience with Verilog and/or VHDL, programming/scripting (Python, Perl, Ruby, Java, C/C++), and familiarity with IC design tools (Cadence, Synopsys, etc.). Knowledge of AI/ML applications in RTL/verification and exposure to lab equipment (where applicable) are advantageous.

Who we are looking for: a self-driven, curious, and motivated individual who is eager to learn, works well with others, and approaches problems with a positive attitude. A readiness to work hard while engaging with multiple disciplines and teams is valued.

Location: Singapore, Singapore.