Hardware & Silicon Validation Principal Engineer

About the Role The Hardware & Silicon Validation group seeks a Principal Engineer to lead electrical characterization, compliance, and debug for high-speed SerDes IP (Ethernet 802.3ck/dj and PCIe Gen5/Gen6) across data center products. You will own the validation strategy, drive lab measurements and automation, and collaborate with design, product, and customer teams to ensure production-ready, high-quality silicon.

What You'll Do

• Lead electrical characterization, compliance, and debug for SerDes IP targeting Ethernet IEEE 802.3ck/dj and PCIe Gen5/Gen6 standards at 112G/224G data rates.
• Develop and implement automated validation methodologies, regression frameworks, and compliance test plans for SerDes interfaces across multiple product lines.
• Drive signal integrity analysis and optimization for high-speed channels, including correlation between pre-silicon modeling, simulation, and lab measurements.
• Own the end-to-end SerDes validation strategy for assigned product programs, from test plan development through production readiness sign-off.
• Provide technical leadership and applications engineering support to strategic customers, including on-site debug and performance optimization.
• Define and manage equipment CAPEX plans for advanced test equipment; ensure measurement infrastructure readiness for current and next-generation SerDes IP.
• Mentor and develop staff-level and junior engineers in high-speed signal integrity measurement techniques, debug methodologies, and test automation best practices.
• Collaborate closely with SerDes design, architecture, and product engineering teams to drive silicon quality from early bring-up through volume production.
• Contribute to high-speed board design reviews, extraction, and characterization; partner with internal tools teams to build robust test infrastructure.
• Author technical collateral including validation reports, application notes, and best-known-methods documentation for internal and customer use.
• Represent Marvell in industry forums and customer technical reviews; contribute to standards awareness for IEEE 802.3 and PCI-SIG specifications.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 8+ years of relevant industry experience; or Master’s/PhD with 5+ years of professional experience.
• 5–7+ years of direct experience in SerDes characterization, design, or signal integrity engineering.
• Deep expertise in Ethernet IEEE 802.3ck/dj electrical compliance and validation, and/or PCIe Gen5/Gen6 specifications.
• Strong knowledge of signal integrity principles, channel modeling, S-parameter analysis, equalization architectures (CTLE, DFE, FFE), and board-level design for high-speed interfaces.
• In-depth working knowledge of test equipment used for SerDes characterization: real-time and sampling oscilloscopes, BERTs, vector network analyzers, pattern generators, and protocol analyzers.
• Strong proficiency in Python scripting for test automation, data analysis, and regression infrastructure development.
• Demonstrated ability to lead technical projects and mentor engineers.
• Experience correlating pre-silicon simulations with post-silicon measurements and driving closure on discrepancies.
• Experience with high-speed PCB design, SI simulation tools (HFSS, ADS, Sigrity, or equivalent), and channel extraction methodologies is preferred.
• Active participation or familiarity with IEEE 802.3 or PCI-SIG standards committees is preferred.
• Critical thinking and problem-solving attitude with ownership of the group’s results.
• Excellent verbal and written communication skills; ability to present technical content to customers and executive leadership.

Nice to Have

• Experience with high-speed board design and test methodology in a data center, AI accelerators, or related environments.
• Direct customer-facing experience and on-site debug expertise.

Compensation & Benefits

• Base pay range: USD 150,680 – 225,700 per year.
• Employee stock purchase plan and a comprehensive benefits package supporting financial well-being, family support, mental and physical health, and recognition.