About this role
About the Role Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Manager to lead the development of cutting-edge memory test solutions. The role focuses on guiding FPGA architecture, design, and verification to deliver reliable, high-performance test platforms. The candidate will collaborate with cross-functional teams to accelerate innovation and impact across Teradyne's product portfolio. What You'll Do
- Lead the FPGA development effort for memory test solutions and manage a team of engineers.
- Architect, design, implement, and verify high-performance FPGA blocks used in test platforms.
- Collaborate with software, hardware, and product teams to define requirements, schedules, and quality metrics.
- Drive project execution, ensure on-time delivery, and maintain robust documentation and design practices. What We're Looking For
- Proven experience in FPGA design (Verilog/VHDL) and a track record of leading engineering teams.
- Strong background in memory test or related test-device domains is highly desirable.
- Excellent collaboration, communication, and problem-solving skills; able to work across disciplines.
- Bachelor's or higher degree in Electrical Engineering or a related field (or equivalent experience). Nice to Have
- Experience with Teradyne Memory Test solutions or other test equipment.
- Familiarity with memory interfaces and memory test methodologies; exposure to DFT/scan architectures.
- Experience in fast-paced hardware development environments.