Experienced Engineer - ASIC Backend Synthesis

Experienced Engineer - ASIC Backend Synthesis

Bangalore, Karnataka, India

Job description

Company and benefits

Job ID 786757

Grow with us

Join Ericsson’s cutting-edge journey to shape the future of 5G networks! As you’ll work on pioneering digital ASIC designs vital to Ericsson’s mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you’re passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you.

At Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you’ll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom!

We are hiring a Physical Synthesis Engineer to own the synthesis flow and constraint development on high-performance, low-power SoC designs. Your primary focus will be physical-aware synthesis, floorplan-driven netlist optimization, and QoR closure — while also contributing to static timing analysis (STA) signoff as well. You will work closely with RTL design, place-and-route, and DFT teams throughout the full design cycle.

What you will do:

Physical-Aware Synthesis (PAS)

• Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout timing and congestion surprises.
• Integrate synthesis with P&R tools for early physical feedback loops — congestion-aware optimization, placement-aware buffering, and pre-CTS timing.
• Collaborate with P&R engineers on DEF/floorplan hand-off; iterate on netlist quality to reduce downstream ECO effort.
• Perform flat and hierarchical synthesis for large designs; manage partitioning and interface timing budgets.
• Perform formal or equivalence check on the netlist at block or top level.

QoR & Optimization

• Track and report key QoR metrics — timing slack, area, cell count, power — across design iterations and process corners.
• Identify and resolve synthesis bottlenecks: critical path restructuring, datapath optimization, and register retiming.
• Provide RTL coding guideline feedback to design teams to improve synthesizability and QoR from the source.
• Manage technology library characterization inputs: Liberty (.lib), LEF, and UPF/CPF for multi-voltage designs.
• Own synthesis QoR sign-off checklist and contribute to tape-out readiness reviews.

Static Timing Analysis

• Run block-level and full-chip STA using PrimeTime (PT) for timing analysis across PVT corners.
• Support MMMC (Multi-Mode Multi-Corner) timing closure; analyze and triage timing violations with P&R and synthesis teams.
• Review and validate SDC constraints developed during synthesis against post-layout STA results.
• Contribute to clock domain crossing (CDC) checks and timing exception audits during signoff.

The skill you bring:

• 5+ years in physical synthesis or logic design implementation
• Expert-level use of Fusion Compiler
• Strong SDC constraint authoring and management skills
• Experience with physical-aware synthesis flows and P&R hand-off
• Working knowledge of STA (PrimeTime)
• Proficiency in Tcl; Python scripting a strong plus
• At least one tape-out on 7nm or below

Nice to have:

• Familiarity with low-power methodologies (UPF/CPF, multi-Vt, clock gating)
• Understanding of PTPX-based power analysis flows
• DFT synthesis experience (scan, BIST, boundary scan)
• Familiarity with congestion-aware and timing-driven P&R closure

EDA Tools & Environment

• Design Compiler, Fusion Compiler, Synopsys PrimeTime, Formality, Tcl/Python.

“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”