About this role
Job title: Distinguished Engineer - Memory Subsystem Center of Excellence (CoE), Custom Silicon
About the Role The Distinguished Engineer, Memory Subsystem CoE, is the senior-most technical authority responsible for end-to-end memory subsystem development across all programs, customers, and SoCs. The role ensures platform-ready, reusable memory subsystems aligned to JEDEC standards and long-term roadmaps, partnering with Architecture, SoC teams, PCIe/Ethernet/Security CoEs, PHY vendors, and customers to enable quality, predictability, and scalable delivery.
What You'll Do
- Own the Memory Subsystem TFM and technical roadmap across current, next-generation (N+1), and future (N+2) platforms.
- Act as the final technical authority for architecture, micro-architecture, RTL, DV, PHY integration, and system validation decisions.
- Define and maintain reference architectures, configuration models, and integration guidelines for memory subsystems.
- Drive sign-off criteria, quality gates, and KPIs across architecture, DV, and validation.
- Partner with Memory CoE leadership to ensure consistent execution across multiple programs and sites.
- Guide cross-functional teams (architecture, RTL, DV, PHY, FW/SW, validation) to deliver reusable, platform-quality subsystems—not point solutions.
- Review and resolve cross-program technical issues and escalations.
- Serve as the first technical point of contact for customers on memory subsystem architecture, features, and roadmap.
- Engage with ecosystem partners (JEDEC, IP vendors, PHY providers) on standards adoption, interoperability, and enablement.
- Support customer engagements, design reviews, and post-silicon debugging when required.
- Align memory subsystem evolution with SoC, compute, AI, and interconnect roadmaps across the company.
What We're Looking For
- 10+ years of experience in memory subsystem, SoC, or IP development.
- Expertise in DDR4/DDR5, LPDDR5/5X, and/or HBM architectures and system integration.