Digital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026)

Job title: Digital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026)

About the Role Marvell’s Digital Logic & Design Verification Graduate Co-Op Program offers hands-on experience developing next-generation semiconductor technologies. This role is designed for students interested in digital IC design, SoC architecture, and verification methodologies, working on high-performance chips used in the scale up and scale out of AI data centers and other enterprise level applications. Co-ops will gain exposure across the design lifecycle—from RTL development to simulation, verification, and silicon validation—while collaborating with cross-functional engineering teams.

What You'll Do

• Contribute to RTL design and implementation of digital logic blocks for ASICs/SoCs for our next-generation products
• Support micro-architecture development, design specification, and implementation
• Assist with synthesis, timing analysis, and design reviews
• Collaborate with verification and physical design teams to ensure design quality
• Develop and execute verification test plans for digital and SoC designs
• Build simulation environments, testbenches, and verification components
• Debug simulation failures and analyze coverage
• Work closely with design engineers to ensure functional correctness and performance
• Use industry-standard tools such as Verilog/SystemVerilog, UVM, and scripting languages
• Automate workflows and analyze data using Python or similar tools
• Support end-to-end chip development from architecture through validation
• Collaborate with global engineering teams on leading-edge semiconductor products

What We're Looking For

• Currently enrolled in a Master’s or PhD program in Electrical Engineering, Computer Engineering, or a related field
• Strong foundation in digital logic design and computer architecture
• Familiarity with HDL languages such as Verilog or SystemVerilog
• Strong problem-solving, analytical, and communication skills

Nice to Have

• Exposure to UVM or formal verification methodologies
• Experience with RTL design, simulation, or FPGA-based projects
• Knowledge of scripting languages (Python, Perl, TCL, or shell)
• Familiarity with SoC design concepts or high-speed interfaces (e.g., PCIe, DDR)
• Prior internship or academic project experience in digital design or verification

Compensation & Benefits

• Expected Base Pay Range (USD) 35 - 70 per hour
• Medical, dental, and vision coverage; robust mental health resources; paid holidays
• Additional compensation may be available for intern PhD candidates