Digital IC Design Junior Engineer

About the Role Join Marvell's Coherent DSP BU as a Digital IC Design Junior Engineer, helping to design high-performance DSP ASICs shipped to top hyper-scale networks. You will work on RTL design, verification planning, and IP block prototyping to drive product development from architecture to silicon. What You'll Do

• Analyze product specifications and architectural requirements to drive design and verification planning for high-speed communication chips.
• Design and develop RTL modules in Verilog/SystemVerilog alongside C++, Python, and Linux-based tooling and firmware.
• Prototype next-generation IP blocks to assess feasibility and de-risk future product development.
• Maintain and enhance silicon-proven RTL and firmware within existing Marvell product lines, ensuring functional correctness and performance.
• Develop and execute verification strategies including unit, integration, and regression testing using Python-based frameworks. What We're Looking For
• Education: Bachelor's degree in Electronics, Computer, or Telecommunications Engineering.
• Hands-on experience in digital design and RTL development; familiarity with chip development flows and verification methodologies.
• Technical knowledge: Proficiency in C, C++, and Python; working knowledge of Verilog, SystemVerilog, or VHDL; solid understanding of Object-Oriented Programming principles.
• Skills: Ability to work independently and in cross-functional teams; strong analytical and problem-solving skills; comfortable engaging across organizational levels and technical disciplines.
• Languages: English (Intermediate–Advanced); Spanish (Native or fluent). Nice to Have
• Experience with Linux-based tooling and firmware. Compensation & Benefits
• Competitive compensation and great benefits. Work environment: collaborative, transparent, and inclusive. Opportunity to grow and develop with us. For more information, visit the Careers page.