Digital DFT Design Engineer

About the Role This is an opportunity to join a top-notch Power Management IC Team with Renesas leading Automotive Business Unit. You will be part of a highly skilled group building world-class automotive PMIC products that will power tomorrow’s automobiles. You will design complex chips that include various analog and digital control circuitry and work closely with all aspects of chip design – from writing specifications to developing tests for mass production. What You'll Do

• Insert DFT/Scan on digital logic and ATPG; validate test patterns on pre- and post-layout gate-level netlists.
• Deliver test patterns to the TEST engineering team and validate them on silicon.
• Insert LogicBIST with industry-standard tools; improve scan coverage; modify RTL for scan; reduce test time.
• Gain exposure to automotive test requirements (ASIL) and participate in all design-flow areas: architecture, RTL Verilog/SystemVerilog design, DFT, timing constraints, synthesis, P&R, timing analysis, lint, CDC.
• Work closely with Architects, Design, P&R, Test, and Silicon Validation; assist with top-level test benches for scan; run gate-level simulations.
• Develop detailed design documents and help write DFT specifications and collateral; participate in design reviews and checklists.
• On-site presence for 3 days a week is required. What We're Looking For
• Required: Master’s with 6+ years or Bachelor’s with 8+ years in digital DFT design; strong DFT fundamentals; able to work independently and as part of a team.
• Hands-on experience in Scan insertion, improving scan coverage, ATPG; experience in LogicBIST; gate-level simulations with test patterns; basic digital RTL coding; at least 2 tapeouts with DFT/Scan.
• Familiarity with industry-standard tools (Synopsys, Cadence, Mentor); Tetramax experience is a huge plus.
• Attention to detail, accuracy, and strong communication; cross-functional collaboration; analytical mind.
• Nice to have: knowledge of Verilog, Verilog-AMS, SystemVerilog; revision control (Git, SVN, SOS); exposure to I2C, SPI, AMBA PMICs and regulators. Nice to Have
• Experience contributing across several silicon tapeout cycles; domain knowledge in PMICs and regulators; Verilog/SystemVerilog proficiency; UVM/verification exposure. Compensation & Benefits
• Salary and benefits are not disclosed in the posting.