DFT Manager

About the Role Marvell is seeking a DFT Manager to lead the definition, implementation, and execution of Design for Test (DFT) strategies across complex silicon designs. This role ensures high test coverage, manufacturability, and product quality while balancing cost, schedule, and performance, and leads a team of DFT engineers across cross-functional partnerships.

What You'll Do

• Own and define the overall DFT architecture and methodology for SoCs, ASICs, or IP blocks across multiple programs.
• Develop and maintain DFT best practices, automation flows, and documentation.
• Lead the planning, insertion, and validation of DFT features such as: Scan (full scan, compression, EDT); ATPG and fault modeling (stuck-at, transition, cell-aware, path delay); BIST (logic BIST, memory BIST); Boundary scan (IEEE 1149.x), IJTAG, and DFT for IOs and analog blocks.
• Ensure high test coverage while minimizing area, power, and timing impact.
• Drive testability requirements from early architecture through tape-out.
• Review and sign off on DFT readiness at key milestones (RTL freeze, netlist, tape-out).
• Collaborate with: Design and physical teams to resolve DFT timing, congestion, and implementation issues; Product engineering and manufacturing to support silicon bring-up, yield learning, and volume production; ATE and test program teams for test pattern delivery and deployment.
• Manage and mentor a team of DFT engineers, including: Technical direction and design reviews; Performance management and career development; Interface with EDA vendors on tool usage, flows, and feature requirements.

What We're Looking For

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of hands-on DFT experience with increasing technical or leadership responsibility.
• Strong expertise in: Scan architecture and ATPG methodologies; Memory and logic BIST; Fault coverage analysis and debug; DFT insertion and verification flows.
• Solid understanding of: Digital design and verification; Timing, power, and physical design interactions; Silicon manufacturing and test processes.
• Proficiency with Tessent EDA tools.
• Experience taking multiple designs from concept to tape-out.