About this role
Job title: Design Verification Senior Staff Engineer
We are seeking a Design Verification Senior Staff Engineer to contribute to the verification of Marvell's next-generation network switches. The role focuses on driving functional verification of complex networking blocks and contributing to verification methodology and infrastructure in a fast-paced environment.
Drive functional verification of complex networking blocks using UVM/SystemVerilog. Develop and maintain advanced verification components and testbenches. Collaborate with cross-functional teams including architecture, design, firmware, and post-silicon. Contribute to methodology and infrastructure improvements in a dynamic and innovative environment.
B.Sc. or M.Sc. in Electrical/Computer Engineering. 7+ years of hands-on experience in ASIC/RTL verification. Strong background in SystemVerilog and UVM methodology. Deep understanding of coverage-driven verification, object-oriented programming, and constrained random testing. Excellent problem-solving skills and self-learning ability.
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.