About this role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
JOb Profile
This is a unique opportunity to join the HPP IP R&D Group at Cadence Design Systems. We are looking for a Sr Principal SI/PI Engineer who will be a key contributor to our advanced high speed IP products. This is a hands-on technical position.
Main Job Tasks and Responsibilities:
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Work on test chip package design SI/PI optimization and verification.
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Work on evaluation board design optimization for best SI/PI performance.
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Provide extracted and measured channel models for chip designers in the R&D team.
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Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries.
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Review customer package and board designs and simulation results. Help with providing feedback to customers to ensure best possible performance of our IP in their ASIC.
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Work on link performance simulations using S-parameter channel models and IBIS-AMI behavioral models.
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Help with SI/PI related debug of test chips or customer ASICs in the lab. Position Requirements:
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M.S. or Ph.D. Electrical Engineering (or similar degree)
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15+ years of experience preferably working with high speed SerDes and PHYs
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Good understanding of high speed SerDes architecture
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Hands on lab experience with instruments like high speed oscilloscopes, TDRs, VNAs, spectrum analyzers, etc.
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Fluent with using 3D and 2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwave
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Experience with IBIS-AMI model simulations
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Experience with simulation result to lab measurement correlation
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Good understanding of PCB and FCBGA design rules and requirements
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Strong debugging and problem-solving skills
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Excellent communication and presentation skills to effectively communicate with both customers and internal stake holders