About this role
About the Role We are seeking a highly skilled Custom Layout Engineer to play a key role in delivering high-quality analog and mixed-signal IP for our chiplet-based solutions. You will take ownership of layout execution from early planning through tape-out, working closely with analog designers to ensure performance, robustness, and manufacturability across advanced technology nodes. What You'll Do
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Analog & AMS Layout Ownership: Lead layout activities for analog, mixed-signal, and AMS blocks and macros, ensuring high-quality, robust, and manufacturable implementations.
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Advanced Node Layout: Apply low-parasitic and high-frequency layout techniques across planar and FinFET technologies, ensuring performance and reliability at advanced nodes.
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Verification & Sign-off: Perform and support DRC, LVS, extraction, EMIR, ESD/LUP, and PERC verification, addressing issues efficiently and thoroughly.
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Collaboration with Design Teams: Work closely with analog and mixed-signal designers to understand circuit intent, constraints, and trade-offs, translating them into optimal physical implementations.
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Scripting & Automation: Develop and maintain scripts (e.g. Skill/TCL) to improve layout productivity, consistency, and quality.
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Mentorship & Technical Leadership: Mentor junior layout engineers, sharing best practices and contributing to continuous improvement of layout methodologies and flows. What We're Looking For
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Bachelor's degree in Electrical Engineering or related field
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5–10+ years of experience in analog IC layout
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Strong understanding of analog layout concepts, parasitics, and high-frequency design techniques
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Proven experience delivering blocks and macros to successful, high-quality tape-out
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Hands-on experience with planar technologies (e.g. 28/22 nm) at TSMC and/or GlobalFoundries
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Hands-on experience with FinFET technologies (e.g. 16/7/6 nm) at TSMC
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Exposure to multiple foundries (e.g. TSMC, Samsung, GlobalFoundries)
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Proficiency with Cadence Virtuoso, Synopsys Custom Compiler, and physical verification tools such as Calibre and ICV
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Experience with EMIR, ESD/LUP, and PERC verification flows
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Skill and/or TCL scripting experience
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Soft & Professional Skills:
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Clear, structured communication in professional English—able to explain complex results concisely
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Collaborative and feedback-oriented mindset
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Demonstrated ability to mentor and guide less experienced engineers
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Strong ownership, reliability, and follow-through
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Curious, self-motivated attitude, eager to learn and explore new tools or methods
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High level of integrity and professionalism Compensation & Benefits
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Remote-first flexibility – work from anywhere with flexible hours
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Equipment & setup – tools provided to succeed
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High-impact projects – design real analog IP used in customer silicon
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Supportive team culture – dedicated manager and collaborative colleagues
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Competitive, transparent compensation – adjusted for your location
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Learning & growth opportunities – AI–DLP sessions and more