About this role
About the Role Lead end-to-end custom IC mask/layout design for analog, RF, and mixed-signal circuits at 40/22nm nodes. Drive layout development from concept to tapeout and mentor junior engineers, providing technical guidance on floorplanning, placement, routing, shielding, matching, and layout optimization. What You'll Do
- Lead end-to-end layout development for blocks/IP/chip from concept to tapeout.
- Collaborate with junior engineers and contractors to schedule tasks, guide floor planning, implementation reviews, and closure.
- Work with design engineers and CAD support to maintain effective communication and ensure quality deliverables.
- Review and approve layouts for quality, DRC/LVS/PEX closure, EM/IR compliance, ESD robustness, and manufacturability.
- Develop methods to improve efficiency in layout methodology and drive best practices for reliable and timely outputs.
- Apply expertise in floorplanning, placement, routing, shielding, matching, and LDE to meet performance and fabrication requirements. What We're Looking For
- Bachelor’s or Master’s Degree with 10-12 years of relevant experience.
- Strong proficiency in Cadence Virtuoso XL for layout and Calibre for DRC/LVS/PEX.
- In-depth understanding of CMOS IC mask design and verification, with knowledge of fabrication, electromigration, IR drop, coupling capacitance, device and signal matching, and Layout-Dependent Effects (LDE).
- Self-driven professional with effective planning and reporting capabilities.
- Excellent collaboration and communication skills to coordinate with design engineers, CAD support, junior engineers, and contractors.