CPU Physical Design Engineer

About the Role Intel's CPU development team is seeking a CPU Physical Design Engineer to perform physical design implementation of custom CPU cores and drive manufacturing-ready design databases. You will contribute to power-efficient, high-performance CPUs across Intel's compute roadmap and collaborate with multiple engineering teams. What You'll Do

• Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
• Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
• Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.
• Optimizes CPU design to improve product level parameters such as power, frequency, and area.
• Participates in the development and improvement of physical design methodologies and flow automation. What We're Looking For
• Minimum Qualifications: Bachelors in Computer Engineering or Electrical Engineering or related field with 6+ years of relevant work experience or MS in Computer Engineering or Electrical Engineering or related field (or higher degree) with 4+ years of relevant work experience.
• 4+ years' experience in Synthesis of a digital logic block or partition.
• At least 1 Completion of Tape Out on advanced technologies.
• 4+ years of experience in each of the following: experience with IC design tools (e.g., Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure; PV convergence (including static timing and power analysis); chip physical design verification including formal equivalence, electrical rules, DRC/LVS, and Noise flow; scripting with TCL.
• Preferred Qualifications: 8+ years of Tape Out experience.
• Strong knowledge with Physical design best known practices concerning floor-planning, routing techniques, clock distribution.
• Strong knowledge of Static Timing Analysis, Noise analysis, and reliability verification techniques.
• Strong knowledge of RTL to GDS methodologies and formal equivalence.
• Experience performing CPU level timing analysis and optimization, ensuring designs meet functional and performance requirements.
• Experience generating and verifying timing constraints while addressing timing violations at the chip or block level for CPU cores.
• Experience working closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning. Nice to Have
• Tape Out experience with 8+ years.
• Excellent knowledge of floor-planning, routing, clock distribution.
• Deep experience with STA, Noise analysis, reliability verification techniques.
• RTL to GDS methodologies and formal equivalence.
• CPU level timing analysis and optimization.
• Ability to generate timing constraints and address timing violations at multi-block/chip level. Compensation & Benefits
• Our total rewards package goes above and beyond just a paycheck. We offer generous benefits to help you build your career, health, and wealth. For details of benefits available to you, visit Intel Benefits | Intel Careers. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.