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Next Gen CPU Power Management RTL Design Engineer
Advanced Micro Devices
onsiteUSD 166,400 - 249,600 / year
Santa Clara, California
About this role
Next Gen CPU Power Management RTL Design Engineer
Location: Santa Clara, CA, USA
Work Authorization: This role is not eligible for visa sponsorship.
Key Responsibilities
- Design and develop microarchitecture for core clocking, reset, and power management IP in next-generation processors.
- Collaborate with architecture, design verification, physical design, and firmware teams to integrate IP into the overall processor using cutting-edge process technologies.
- Define specifications and documentation for IP microarchitecture and interfaces.
- Implement RTL in Verilog/SystemVerilog optimized for timing, area, power, and performance.
- Develop C/C++ firmware for IP initialization, configuration, and control; partner with firmware engineers to ensure seamless integration.
- Perform RTL linting, clock domain crossing (CDC) analysis, and related checks for design correctness.
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