Principal RTL Design Engineer
About this role
About the Role The Principal RTL Design Engineer will contribute to RTL design and verification of DDR/Flash controller and PHY subsystems within Microchip’s Mixed-Signal Development Group, driving ASIC development from design through silicon bring-up. You will collaborate with architects, verification, firmware, and backend teams to deliver high-performance mixed-signal IP and ensure robust integration across Microchip products. What You'll Do
- Participate in the full ASIC design cycle, including design, verification, backend implementation, silicon bring-up and debugging.
- Design RTL using Verilog/SystemVerilog, integrate IP blocks, and implement supporting logic (clock/reset, JTAG, DFT, SRAMs, etc).
- Run clock domain crossing (CDC) analysis, lint checks, and power simulations.
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