Principal Analog Layout Engineer
About this role
About the Role Join Marvell's Central Engineering as a Principal Analog Layout Engineer, contributing to the layout of analog/mixed-signal components for Marvell's High-Speed SerDes IPs. The role supports validation of HSS IPs in the lab and collaborates with the AMS-IP team to deliver leading-edge SerDes PHY solutions across multiple applications. What You'll Do
- Layout analog/mixed-signal circuits for High-Speed SerDes IPs within Marvell's AMS-IP team and Central Engineering.
- Collaborate with design, verification, and lab teams to validate layouts in lab environments and ensure accurate parasitic extraction.
- Ensure layout quality, DRC/LVS compliance, and performance of SerDes blocks across process nodes, interfaces, and packaging.
- Support fast SoC production through close coordination with Central System Engineering and business units. What We're Looking For
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